In recent semiconductor integrated circuit devices, a vast number of semiconductor devices are formed on a common substrate, and a multilayer interconnection structure is used for interconnecting these semiconductor devices.
In a multilayer interconnection structure, a plurality of interlayer insulation films are laminated with each other wherein each of the interlayer insulation films includes an interconnection pattern that constitutes an interconnection layer in the form embedded therein. In such a multilayer interconnection structure, a lower interconnection layer is connected to an upper interconnection layer via a via-contact formed in an interlayer insulation film.
In recent ultra-miniaturized or ultra high-speed semiconductor devices, a low dielectric film (so-called low-K dielectric film) is used for the interlayer insulation films for reducing the problem of signal delay (RC delay) that takes place in the multilayer interconnection structure. Further, together with this, low resistance copper (Cu) patterns are used for the interconnection patterns.
In a multilayer interconnection structure in which a Cu interconnection pattern is embedded in a low-K interlayer insulation film, a so-called damascene process or dual damascene process is used extensively in view of the difficulty of patterning a Cu layer by way of dry etching process. In a damascene process or dual damascene process, interconnection trenches or via-holes are formed in the interlayer insulation film in advance, and a Cu layer is formed so as to fill the interconnection trenches or via-holes thus formed. Further, excessive Cu layer on the interlayer insulation film is removed by a chemical mechanical polishing (CMP) process.
In order to avoid the problem of short circuit or the like caused in such a structure by the Cu atoms invading into the interlayer insulation film by diffusion, which tends to occur when the Cu interconnection pattern has made a direct contact with the interlayer insulation film, it is practiced in the art to cover the sidewall surfaces and bottom surface of the interconnection trenches or via-holes, on which the Cu interconnection patterns are to be formed, by a conductive diffusion barrier or so-called barrier metal film, and to deposit the Cu layer on such a barrier metal film. For such barrier metal films, a refractory metal such as tantalum (Ta), titanium (Ti), Ruthenium (Ru), or the like, is used. Alternatively, a conductive nitride of such a refractory metal or stack of these films may be used.